1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to semiconductor devices having arranged multiple standard cells.
2. Description of the Background Art
For designing semiconductor devices, in the 45 nm generation in particular, there has been adopted or considered a technique for designing referred to as a restrictive design rule (RDR). More specifically, the RDR is a design rule with severe constraints. It does not employ a two dimensional layout having a metal wiring and a poly wiring each bent. Rather, it employs a one dimensional layout prohibiting such bending. This reduces or eliminates variation attributed to dependency on geometry of transistors, wirings and the like, and furthermore, reduces or eliminates design rule check (DRC), optical proximity correction (OPC), lithography verification and other similar electronics design automation (EDA) loads. The RDR can thus reduce or eliminate variation in lithography, and complicated designs.
Furthermore when a semiconductor device is designed, a standard cell may be used, for example as disclosed in Japanese Patent Laying-open No. 06-085062. In particular, a standard cell is used to design a layout, for example as disclosed in Japanese Patent Laying-open No. 2000-277620, to accommodate a system-on-chip (SOC) with a circuit increased in scale.
Furthermore, reducing the number of contacts for electrical connection has been proposed to provide a highly integrated SOC. For example, Japanese Patent Laying-open No. 2005-079594 describes that a first active region provided with a metal oxide semiconductor (MOS) transistor and a second active region provided for a first voltage are connected by a third active region to achieve a reduced number of contacts.
Furthermore, a finer pattern has been promoted for a further highly integrated SOC. This results in making it difficult to ensure resolution in lithography for the 45 nm or 32 nm or later generation in particular. This has been handled by adopting or considering an RDR, which restricts a pitch in arranging a pattern, the pattern's geometry, and the like. The RDR stabilizes lithography and thus alleviates variation attributed to dependency on geometry of transistors, wirings and the like (see Japanese Patent Laying-open No. 2000-223663 for example).
When an RDR with a severe design constraint is applied to a standard cell, the standard cell is increased in area. This problem is remarkable in particular for general SOC products, which have a chip having a large area occupied by standard cells. In other words, the chip has a major area occupied by standard cells having an increased area, and as a consequence, the chip is increased in size, resulting in a semiconductor device increased in size and cost.
Furthermore, simply making a cell that has conventionally been used fine in a design for the purpose of highly integrating a semiconductor device has resulted in insufficient resolution and increased variation in lithography. There has not been a sufficient proposal for a method applying the RDR to a cell to resolve such issues in lithography.